1. Field of the Invention
The present invention relates to a semiconductor memory device in which an improvement is made in a decoder portion including spare decoders. Particularly, the present invention relates to a semiconductor memory device in which if a fault occurs in a memory cell connected to a normal decoder, the decoder connected with the faulty memory cell is separated to be in a non-selective state and a spare decoder in place thereof is brought into a selective state to be substituted for the above stated normal decoder, using a laser program system.
2. Description of the Prior Art
A semiconductor memory device, integrated to a high degree according to the recent trend, is generally provided with spare memory cells and spare decoders connected to the spare memory cells, so that even if a fault is caused in a part of memory cells in the manufacturing process thereof, the device as a whole can be protected from malfunctioning due to such fault. More specifically stated, such a semiconductor memory device is in a so-called redundancy structure in which if a fault is detected in a certain normal memory cell, a normal decoder connected therewith is separated to be in a non-selective state and a spare decoder is brought into a selective state in place of the normal decoder.
In a memory device of such a redundancy structure, a laser program system is often adopted as a method for operating a spare memory cell by separating the normal decoder concerned and bringing a spare decoder into a selective state in case where a fault is detected in a normal memory cell. In such a laser program system, a laser beam is applied to specified link elements, whereby the normal decoder associated is separated and a spare decoder is brought into a selective state.
For example, in "Laser Programmable Redundancy and Yield Improvement in a 64K DRAM" by R. T. Smith et al. in IEEE J. Solid-State Circuits, vol. SC-16, pp. 506-513, October 1981, a semiconductor memory device of a redundancy structure to which a laser program system is applicable is described. This document indicates, as factors constituting obstacles to accurate application of a laser beam to link elements, the following three points:
(1) effective spot diameter of a laser beam,
(2) dimensions of link element and (3) distance between link elements, and points out problems caused in case of a high degree of integration of a memory device.
In "A Low-Power Sub 100ns 256K Bit Dynamic RAM" by S. Fujii et al. in IEEE J. Solid-State Circuits, vol. SC-18, pp. 441-445, October 1983, an example of a semiconductor memory device of a redundancy structure using a laser program system is disclosed. The device disclosed in this document does not comprise link elements for each word line so as to be adapted for a high degree of integration; however, this device involves demerits such as slow speed of operation.
In "A 256K Dynamic RAM with Page-Nibble Mode" by K. Fujishima et al. in IEEE J. Solid-State Circuits, vol. SC-18, pp. 470-478, October 1983, the prior art of most interest to the present invention is disclosed. For the purpose of clarifying the essential feature of the present invention, the art described in this document will be described concretely and briefly with reference to FIGS. 1 to 4.
FIG. 1 is a plan view illustrating a typical structure of a semiconductor memory device.
Referring to FIG. 1, a semiconductor memory device comprises memory cell array portions 1a, 1b, 1c and 1d and a decoder portion 2 associated with the memory cell array portions 1a to 1d. To the semiconductor memory device, an external reference signal RAS and external address signals A.sub.0 to A.sub.n are applied from the outside. These signals are supplied to the decoder portion 2 through a specified circuit group.
The above stated specified circuit group is structured by, for example, an RAS buffer circuit 3 for providing an internal reference signal (RAS signal) based on an external reference signal RAS, an RQ circuit 4 for providing a clamp signal (an RQ signal), an address buffer circuit 5 for address signals, a word line driver circuit 6, a sub-decoding circuit 7, a delay and inversion circuit 8 for providing an RXD signal and a delay and inversion circuit 9 for providing an RXDD signal. The signals supplied from the outside to the memory device are converted into signals suited for the decoder portion 2 by means of these circuits and base on the signals supplied from the outside, necessary signals are provided for the decoder portion 2.
FIG. 2 is a detailed plan view illustrating the array portions 1a to 1d and the decoder portion 2. The array portions 1a to 1d include a plurality of word lines represented by the dotted lines extending horizontally and a plurality of bit lines represented by the solid lines extending vertically and intersecting orthogonally with the word lines. On the respective points of intersection between the word lines and the bit lines, memory cells not shown are disposed.
The decoder portion 2 includes a plurality of column decoders aligned horizontally and a plurality of row decoders aligned vertically. The column decoders include j normal column decoders (1) to (j) and a spare column decoder (S1) on the left in the drawing and a spare decoder (S2) and j normal column decoders (j+1) to (2j) on the right, j being an integer number. From the respective column decoders, two pairs of bit lines BL.sub.L (1), BL.sub.L (1) and BL.sub.L (2), BL.sub.L (2) to BL.sub.L (4j-1), BL.sub.L (4j-1) and BL.sub.L (4j), BL.sub.L (4j) extend upward and two pairs of bit lines BL.sub.R (1), BL.sub.R (1) and BL.sub.R (2), BL.sub.R (2) to BL.sub.R (4j-1), BL.sub.R (4j-1) and BL.sub.R (4j), BL.sub.R (4j) extend downward in the drawing.
The row decoders aligned vertically include k normal decoders (1) to (k) and a spare decoder (S1) on the upper side and a spare decoder (S2) and k normal decoders (k+1) to (2k) on the lower side, k being an integer number. From the respective row decoders, two word lines WL.sub.L (1), WL.sub.L (2) to WL.sub.L (4k-1), WL.sub.L (4k) respectively extend to the left and two word lines WL.sub.R (1), WL.sub.R (2) to WL.sub.R (4k-1), WL.sub.R (4k) respectively extend to the right. These word lines intersect the bit lines as described previously. Memory cells are disposed on the respective intersection points so that four memory cell array portions 1a to 1d are formed.
Referring to FIG. 2, description will be made by taking the right, upper array portion 1c as an example. Now, assuming that a fault is detected in one of the memory cells disposed on the word line WL.sub.R (1) or WL.sub.R (2) extending from the row decoder (1), the memory cells selected by the normal row decoder (1) contain a faulty cell. Consequently, if the normal row decoder (1) is separated to be in a non-selective state and the spare row decoder (S1) is made to function in place, the semiconductor memory device as a whole functions normally. Such structure comprising spare decoders and memory cells associated with the spare decoders is generally called a redundancy structure or a redundancy circuit in a memory device.
In the following, a concrete circuit structure of a decoder will be described by taking an example of a row decoder.
FIG. 3 is a circuit diagram of a normal row decoder for selecting word lines WL.sub.R (k), WL.sub.R (k+1), WL.sub.L (k) and WL.sub.L (k+1).
Referring to FIG. 3, a row decoder circuit is structured by a combination of MOS transistors, so that a word line is selected according to a signal applied thereto. The reference characters 11a, 11b, 11c and 11d denote link elements inserted in the respective word lines and by melting these link elements, an electrically discontinuous state is established. If a fault is found in a memory cell selected by and one of the word lines WL.sub.L (k), WL.sub.L (k+1), WL.sub.R (k) and WL.sub.R (k+1) connected respectively to the link elements 11a to 11d, the link elements associated are melted by a laser beam and the word line selecting the faulty memory cell is made in a non-selective state. The reference character 12 denotes an output line of the row decoder circuit. Transistors T.sub.0 to T.sub.n for discharge of the output line 12 are connected to the line 12.
FIG. 4 shows a spare row decoder circuit to be substituted for the normal row decoder in a non-selective state in association with a faulty memory cell.
Referring to FIG. 4, all the 2n address signals A.sub.1, A.sub.1 to A.sub.n, A.sub.n are applied to the spare row decoder circuit, n being an integer number. The spare row decoder circuit is made in a non-selective state when it is not to be substituted for any one of the normal row decoder circuits. Substitution of the spare row decoder circuit for a normal row decoder circuit is made by selectively melting the n link elements 11e to 11h inserted in the input lines of the address signals in response to an address of a faulty memory cell. More specifically, in order to select an address signal A.sub.1 or A.sub.1, A.sub.2 or A.sub.2, . . . , A.sub.n or A.sub.n according to the address of the faulty memory cell, the n link elements are selectively melted by a laser beam so that the same address signal as for the normal row decoder circuit in a non-selective state is applied to the spare row decoder circuit, whereby the substitution is made. The spare row decoder circuit includes link elements 11a to 11d in the junction points with the word lines in the same manner as in the normal row decoder circuit shown in FIG. 3. As a result, if a fault occurs in a memory cell associated with the spare row decoder circuit, the spare row decoder circuit itself can also be brought into a non-selective state.
However, in such a redundancy structure as described above, link elements 11a to 11d provided in a normal row decoder circuit for separating a word line associated with a faulty memory cell bringing it into a non-selective state are required for each word line. Accordingly, the distribution density of link elements becomes large and disadvantages are involved that the requirements for the positioning precision of a laser beam or the effective beam diameter at the time of melting link elements are too strict and sometimes it becomes practically impossible to melt link elements.